Offer summary

Qualifications:

Bachelor's or Master's degree in Electronics or a related field., 7-10 years of industry experience on live projects., Proficiency in UVM methodology and System Verilog., Experience in leading a team of approximately 5 members for technical project aspects..

Key responsibilities:

Conduct design verification using UVM methodology.

Work on IP level or SoC level design verification.

Collaborate with diverse teams and communicate effectively.

Utilize knowledge of protocols such as PCIe, Ethernet, DDR, or others in verification tasks.

Job description

Job Position: Senior Design Verification Engineer

Relevant Experience: 7-10 Years

Position: Permanent with Codersbrain Technology Pvt. Ltd.

Location: Bangalore

Notice Period: Immediate to 15 Days.

Client: capgemini

Description:

Qualifications

Bachelors or masters degree in Electronics or related concentration

Experience

7-10 years of Industry Experience on live projects

Must Have skills (Technical + Behavioral)

Methodology: UVM
Languages: System Verilog
Verification knowledge is must. Person should have worked on UVM based design verification
Should have expertise in either IP level DV or SoC level DV
Protocol Knowledge: PCIe OR Ethernet OR DDR OR AXI/ SPI/ UART or any other protocol
>7Y Person should have lead a team of ~5 member team for technical side of project
Good oral and written communication skills. This job requires the ability to work effectively within diverse teams.

Good to Have skills (Technical + Behavioral)