Offer summary
Qualifications:
BS degree with 8+ years experience or MS degree with 5+ years experience in digital verification, Excellent SystemVerilog coding skills, Hands-on experience building verification environment using SystemVerilog and UVM, Experience with verification management is a plus, Familiarity with Cadence or Synopsys EDA tools.
Key responsabilities:
- Digital function verification for IC products
- Develop verification plans according to product definitions
- Create verification environments and test cases using SystemVerilog and UVM
- Manage regression and track verification progress
- Support analog behavior modeling for system verification