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Synthesis/STA_Rakesh_Capgemini

Remote: 
Full Remote
Contract: 
Fixed term
Work from: 
India

Offer summary

Qualifications:

4-15 years of experience in synthesis of complex SoCs and writing timing constraints., Experience in formal verification from RTL to netlist with DFT constraints., Knowledge of post-layout STA closure and timing ECOs, especially in technology nodes 45 nm and below., Familiarity with tools such as Design Compiler, RTL Compiler, LEC, CLP, and ETS/PTSI/GT..

Key responsibilities:

  • Handle SoC/subsystem and block-level synthesis activities.
  • Perform LEC, CLP, and timing closure for SoCs and subsystems.
  • Debug CTS issues and balance clocks using PTPX.
  • Ensure compliance with low-power aware implementation standards.

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Job description

STA (Static timing analysis) Engineers: 4 – 15 years
Location:bangalore
Skills: 
Experience in Synthesis of complex SoCs block/ top level and writing timing constraints.
Experience in formal verification RTL to netlist – to- netlist with DFT constraints.
Experience in post-layout STA closure and timing ECOs.
Worked in technology nodes 45 nm and below.
Knowledge of low -power aware implementation is a plus.
Tools: Design compiler, RTL compiler, LEC, CLP, ETS/ PTSI/ GT.
 
Primary Skills:
Able to handle Soc/Subsystem and blocklevel synthesis activities , Soc/Subsystem and blocklevel LEC, CLP and timing closure
 
Secondary Skills:
Able to handle PTPX and debug CTS issues to balance clocks

Required profile

Experience

Spoken language(s):
English
Check out the description to know which languages are mandatory.

Hard Skills

Static Timing AnalysisFormal MethodsChemical SynthesisLow Power DesignCompiler ConstructionOperations Support SystemsLow Power Design

Other Skills

  • Scheduling
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