5+ years of experience in Synthesis and Static Timing Analysis (STA)., Proficient in Logical aware Synthesis and Logical Equivalence check., Strong knowledge of TCL scripting and UNIX environment., Experience in leading and mentoring a team of 4 to 5 members..
Key responsibilities:
Lead the STA and Synthesis processes for design implementation.
Coordinate with design teams on RTL design, Physical design, and DFT.
Fix timing violations and DRCs through manual ECOs and timing closure techniques.
Guide and mentor team members in STA and Synthesis methodologies.
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