Offer summary

Qualifications:

Experience in Low power RTL design and microarchitecture., Proficient in Verilog and familiar with ASIC design tools like VCS and Design Compiler., Knowledge of power estimation tools and scripting languages such as Shell, Perl, and Python., Experience in hardware architecture exploration and familiarity with Machine Learning or DRAM Memory controllers is a plus..

Key responsibilities:

Design and optimize low power RTL and microarchitecture for area and power reduction.

Utilize ASIC design tools for synthesis and timing closure.

Conduct power estimation and performance modeling as needed.

Collaborate with team members on hardware architecture exploration and related projects.

Job description

1. Experience in Low power RTL design, microarchitecture, synthesis, timing closure, power estimation. Should be proficient in Verilog.

2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units, Floating point datapath design is a plus.

3. Should have experience using ASIC design tools such as VCS, Verdi, Design Compiler. Knowledge of power estimation tools(such as Spyglass, PTPX), scripting languages (Shell, Perl, Python), C language is a plus.

4. Experience with hardware architecture exploration, performance modelling will be a big plus. 5. Prior experience in Machine learning/Artificial Intelligence domain and/or DRAM Memory controllers is a plus.

Required profile