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Senior Physical Design Engineer - Contract

Remote:

Full Remote

Contract:

Fixed term

Experience:

Senior (5-10 years)

Work from:

Belgium

Offer summary

Qualifications:

5+ years of experience in ASIC Physical Design, Expertise in EDA tools like Primetime and Innovus, Strong background in timing closure, Proficient in scripting languages such as Python, Tcl, Perl.

Key responsabilities:

Lead physical design tasks from RTL to GDSII
Drive timing closure and perform physical verification

Berkeley Square IT

11 - 50 Employees

See more Berkeley Square IT offers

Job description

Senior Physical Design Engineer

Overview:

As a Physical Design Engineer, you will be a key contributor to the development of their cutting-edge multi-core in-memory compute SoCs. This role involves hands-on responsibility for the entire physical design flow, from RTL to GDSII

You will work closely with RTL and architecture teams to ensure the successful implementation of physical design partitions, utilizing industry-standard tools and methodologies to meet performance, area, and power targets.

Key Responsibilities

Lead physical design tasks, including synthesis, floorplanning, placement, routing, and optimization.
Drive timing closure, including STA and timing optimization.
Perform physical verification (DRC, LVS) and sign-off, ensuring compliance with all design rules.
Handle power analysis, including EMIR sign-off.
Collaborate with cross-functional teams, including RTL, package, and board teams to ensure smooth chip integration.
Script automation for design processes using Python, Tcl, or Perl.

Essential Qualifications

5+ years of experience in ASIC Physical Design, including RTL to GDSII.
Proven expertise in EDA tools such as Primetime, StarRC, Innovus, Design Compiler, ICC2, and Calibre.
Strong background in timing closure, including STA, clock tree synthesis, and optimization.
Experience with IP integration, including memories, IOs, embedded processors, and analog IP.
Proficient in scripting (Python, Tcl, Perl) for automation tasks.

Desirable Skills

Experience with multi-clock, multi-power domain designs.
Familiarity with chip-package-board co-simulation.
Understanding of ESD, latch-up methodologies, and transistor characteristics.
Experience working directly with tool vendors to resolve bugs and influence tool improvements.