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Lead Analog Design Engineer (SERDES)

extra holidays

Remote:

Full Remote

Contract:

Full time

Salary:

58 - 58K yearly

Experience:

Mid-level (2-5 years)

Work from:

Ireland

Offer summary

Qualifications:

BEng, MEng, PhD or equivalent., Minimum of 4 years CMOS design experience., Experience in CMOS SERDES or high-speed I/O IC design preferable., Good understanding of jitter and signal equalization techniques., Proficiency in CAD tools for circuit simulation..

Key responsabilities:

Design High Speed SERDES products up to 112 Gbps.
Develop analog/mixed signal IC circuit blocks from concept to verification.
Collaborate with Physical Design Engineers for circuit block design.
Mentor Junior Design Engineers on project needs.
Work with global teams across different time zones.

Cadence Design Systems Computer Software / SaaS Large

5001 - 10000 Employees

See more Cadence Design Systems offers

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title: Senior Analog Design Engineer (SERDES)

Location: Cork

Reports to: Group Director

Job Overview:

The Cadence Serdes PHY team based at our R&D center of excellence in Cork, is seeking ambitious analog designers who wish to work on the leading edge of Wireline technology at the highest data rates (112Gbps+) and on the smallest technology nodes (e.g. 3nm ).

The PHY team designs products for communication protocols such as PCIe (now at Gen 7) and UCIe (emerging Chiplets standard).

The Senior Analog Design Engineer will take a senior role on the PMA design team as part of a SERDES Product Team.

Job Responsibilities:

Design of High Speed SERDES products at data rates up to and exceeding 112 Gbps on leading edge technology nodes (e.g. 3nm FinFET CMOS)

Design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications

Work closely with Physical Design Engineers to design IC circuit blocks and PMA sections

Work with Technical Team Leads in the areas of circuit design and SERDES architectures

Mentor Junior Design Engineers when the project need arises

Work with global teams (US, west coast and east coast), which work in different time-zones

Job Qualifications:

BEng, MEng, PhD or equivalent.

Candidate’s background should include a minimum of 4 years of CMOS design experience, preferably in the area of CMOS SERDES or high-speed I/O IC design

Should have a good understanding of jitter and signal equalization techniques

Design experience in some of the following SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators

Excellent problem-solving skills, analog aptitude, good communication skills and ability to work cooperatively in a team environment

Position requires proficiency in using CAD tools for circuit simulation, layout and physical verification

Additional Skills/Preferences:

Cadence tool experience and design experience at >10Gbps and in <40nm technologies

Lab test experience as part of silicon evaluation is advantageous

Check out some of our amazing employee benefits at Cadence Ireland

Private Health cover

Lunch Allowance

Sick Pay Scheme

Gym membership

Pension Scheme

Work From Home Allowance

Life Assurance X4 times Salary

Bike to Work Scheme

Employee Stock Purchase Plan (ESPP)

Global Recharge Days

Vacation Days - 25 days per annum

Home internet allowance.

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace. 