Offer summary
Qualifications:
Master’s or Ph.D. in Electrical Engineering, Experience in design of analog/digital circuits preferred, Knowledge of Xcelium, Verilog/VHDL, Familiarity with Cadence Virtuoso, Understanding of advanced verification methodologies.
Key responsabilities:
- Participate in architectural definition and feasibility studies
- Design and integrate digital sub-blocks at top-level
- Support DFT strategy and implementation
- Verification planning and development using Verilog/VHDL
- Lab evaluation, debug of digital blocks and support for production testing