Static Timing Analysis Engineer

Static Timing Analysis Engineer

Mission: Lead the Static Timing Analysis effort; defining methodology, setting up flows and running timing sign-off; within the Physical Design Domain.

Responsibilities & opportunities in this role:

• Lead the Static Timing Analysis efforts within the Physical Design team. 
• Define and own the STA Methodology, signoff criteria, timing margins (PVT variation, jitter, IR drop, aging) which need to be used from Synthesis, P&R to sign-off.
• Work with the CAD team to define and develop the MMMC STA flow for block and full chip STA.
• Work with the CAD team to setup automatic timing ECO generation for block and full chip during ECO/sign-off phase
• Own the leakage/dynamic power recovery with no effect on timing QOR during the ECO phase.
• Perform Full chip and block level constraints validation and analysis and provide feedback to the design/DFT team
• Perform pull up/push down constraints to cross-check against block level interface constraints vs other block interfaces vs top level constraints
• Verify clock network insertions for proper balancing/power reduction with all correct relationship imposed
• Perform timing constraints sign-off (Unconstrained IO’s/State Points, Duplicate timing exceptions, CDC relationship, etc)
• Generate timing convergence/burn down charts for different corners/modes during the signoff phase.

Ideal candidates have/are:

• Bachelors or M.S. in Computer Engineering or Electrical Engineering with 10 or more years of experience in STA; from defining methodology, setting up the tools and flows to running full Chip STA. 
• Strong Knowledge of Multi Mode Multi Corner signoff, process variation, timing margin methodology. 
• Knowledge of timing closure methodologies and best practices, clock domain crossings and clock gating techniques. 
• Proficiency in writing timing constraints and experience with any constraint analyzer tool is a plus. 
• Familiarity with synthesis, P&R, DFT. 
• Experience in setting up and running spice analysis for clock network or custom network
• Experience in industry standard Engineering Design Automation (EDA) or CAD VLSI tools/flows for Static Timing Analysis, Timing ECO generation.
• Excellent coding skills ( TCL, Python)

Attributes of a Groqster:

• Humility - Egos are checked at the door
• Collaborative & Team Savvy - We make up the smartest person in the room, together
• Growth & Giver Mindset - Learn it all versus know it all, we share knowledge generously
• Curious & Innovative - Take a creative approach to projects, problems, and design
• Passion, Grit, & Boldness - no limit thinking, fueling informed risk taking

If this sounds like you, we’d love to hear from you!

Compensation: At Groq, a competitive base salary is part of our comprehensive compensation package, which includes equity and benefits. For this role, the base salary range is $208,000 to $420,400, determined by your skills, qualifications, experience and internal benchmarks.