Offer summary
Qualifications:
10+ years of ASIC engineering experience, Deep knowledge of VLSI/SoC design workflows, Strong programming skills in SystemVerilog, C/C++, Perl, TCL, Python, Expertise in EDA tool support and troubleshooting, Bachelor’s or Master's degree in relevant field.
Key responsabilities:
- Lead EDA tool and workflow development
- Improve and enhance EDA workflows in ASIC team
- Drive optimization for full ASIC chip design
- Collaborate to solve complex technical challenges
- Guide onboarding and support of EDA engineers