Offer summary
Qualifications:
BS or MS in Electrical Engineering or related field, 3-5 years in hardware design development, Expertise in HDLs: Verilog, SystemVerilog, VHDL, SystemC, Proficient in scripting and verification workflows, Experience with UVM environments and Formal Verification.
Key responsabilities:
- Develop and customize hardware design platform
- Generate training data for enterprise LLMs
- Translate research requirements into data insights
- Maintain high standards in coding and documentation
- Collaborate with teams to optimize LLM processes