Offer summary
Qualifications:
4+ years as a Digital Design Engineer, Experience with IP RTL coding for ASIC, Strong skills in Verilog and SystemVerilog, Experience coding for low power in ASICs, BS in Electrical Engineering/Computer Science.
Key responsabilities:
- Own ASIC IP RTL implementation for IP blocks
- Ensure RTL quality with Lint/CDC/RDC checks
- Collaborate with design, architecture, and verification teams
- Supervise RTL-to-GDS flow and integrate blocks into SOC
- Support algorithm analysis and performance requirements