Offer summary
Qualifications:
BS or MS degree in Electrical Engineering or related field, 3-5 years of hardware design development experience, Expertise in Verilog, SystemVerilog, VHDL, and SystemC, Experience with UVM environments and Formal Verification, Knowledge of Lint process and scripting.
Key responsabilities:
- Develop and customize hardware design platform for training data generation
- Collaborate with research teams for data insights
- Maintain standards in coding, debugging, and documentation
- Prioritize needs across teams for performance improvement