Offer summary
Qualifications:
BS or MS degree in Electrical Engineering or related field, 3-5 years of experience in hardware design development, Expertise in HDLs: Verilog, SystemVerilog, VHDL, SystemC, Proficient in scripting and front-end verification workflows, Experience in UVM environments and Formal Verification.
Key responsabilities:
- Develop and customize hardware design platform for LLM training data
- Collaborate with research teams to translate requirements
- Uphold standards in coding, debugging, and documentation
- Coordinate with teams to prioritize needs for LLM performance